[Verilog]7-segment decoder

7세그먼트 디코더

16진수로 표시 0 1 2 3 4 5 6 7 8 9 a b c d E F

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module m_7seg(input [3:0] control,
  output reg [6:0] HEX);
 always@(control[3:0]) begin 
  case(control[3:0])
   4'd0: HEX = 7'b1000000;
   4'd1: HEX = 7'b1111001;
   4'd2: HEX = 7'b0100100;
   4'd3: HEX = 7'b0110000;
   4'd4: HEX = 7'b0011001;
   4'd5: HEX = 7'b0010010;
   4'd6: HEX = 7'b0000010;
   4'd7: HEX = 7'b1011000;
   4'd8: HEX = 7'b0000000;
   4'd9: HEX = 7'b0011000;
   4'd10: HEX = 7'b0100000;
   4'd11: HEX = 7'b0000011;
   4'd12: HEX = 7'b0100111;
   4'd13: HEX = 7'b0100001;
   4'd14: HEX = 7'b0000110;
   4'd15: HEX = 7'b0001110;
   default: HEX = 7'b1111111;
  endcase
 end
endmodule